// $width : input length				//here should never replace !!
// $compress_code : 



`define WIDTH	$width
`define PP_NUM  (WIDTH/2+1)
`define RESULT_WIDTH (`WIDTH*2)
module booth2(
	      input logic [`WIDTH-1:0] i_a,
	      input logic [`WIDTH-1:0] i_b,
	      input logic 	       i_sign
	      );

   wire [`WIDTH-1+1:0] 	  a = {i_sign & i_a[`WIDTH], i_a}; // sign extension for one bit
   wire [`WIDTH-1+2:0] 	  b = {{2{i_sign & i_b[`WIDTH]}}, i_b}; // sign extension for 2 bits
   wire [`WIDTH-1+3:0] 	  b_ext = {b, 1'b0};		    // the 0 after the LSb used for booth2 recoding

   logic signed [`WIDTH:0] pp[`PP_NUM-1:0]; // one bit more than original input i_a
   logic 		  E[`PP_NUM-1:0]; // infact, the last is not needed
   logic 		  S[`PP_NUM-1:0]; // the last is not needed

   //logic [3:0] cols[31:0];
   // logic signed [2:0] 	  booth_array[8:0];	//0, +-1, +-2
   //    
   //logic signed [31:0] 	  result;	//for 16x16
   logic signed [`RESULT_WIDTH-1:0] result;
   

   // ==================== generate PP, S, E ====================
   generate
      genvar 			    i;
      for(i=0;i<`PP_NUM;i++)
	begin : mul_pp
	   Mfxu_mul_smul_igen #(`WIDTH) Fxu_igen_mul
	    (
	     .igen_val (pp[i]),	// the PP
	     .igen_ci(S[i]),
	     .E(E[i]),

	     .u(a),		// the multiplicand 
	     .vx(b_ext[i*2+2:i*2]) // 
	     );
	end // block: mul_pp
   endgenerate

   
   // ==================== PPs compress ====================
   logic [`RESULT_WIDTH-1:0] final_pp0, final_pp1;
   $compress_code;

   

   
endmodule // booth2

   
   
   
   